1. Field of the Invention
The present invention relates to a drive method of a display device.
2. Description of the Related Art
A display element including a current-drive type light emitting portion and a display device including such display element are well known. For example, a display element including an organic electroluminescence light emitting portion (also referred to merely as an organic EL display element in the following description) using electroluminescence (also referred to as EL in the following description) as an organic material receives attention as a display device capable of emitting light with high luminance by low-voltage direct current drive.
For example, in a display device including the organic EL display element (also referred to merely as an organic EL display device), a passive matrix method and an active matrix method are known as drive methods in the same manner as a liquid crystal display device. The active matrix method has a disadvantage that the configuration becomes complicated, however, it has also an advantage that luminance of an image can be increased and the like. The organic EL display element driven by the active matrix method includes, in addition to a light emitting portion having an organic layer and the like including a light emitting layer, a drive circuit for driving the light emitting portion.
As a circuit for driving the organic electroluminescence light emitting portion (also referred to merely as a light emitting portion in the following description), a drive circuit including two transistors and one capacitor unit (referred to as a 2Tr/Ic drive circuit) is known from, for example, JP-A-2007-310311 (Patent Document 1). The 2Tr/Ic drive circuit includes two transistors of a write transistor TRW and a drive transistor TRD, and further includes one capacitor unit C1 as shown in FIG. 2. Here, the other source/drain region of the drive transistor TRD configures a second node ND2 and a gate electrode of the drive transistor TRD configures a first node ND1.
A cathode electrode of a light emitting portion ELP is connected to a second feeding line PS2. A voltage VCat (for example, 0V) is applied to the second feeding line PS2.
As shown in a timing chart of FIG. 4, pre-processing for performing threshold voltage cancel processing is executed in [Period−TP(2)1A]. That is, a first node initialization voltage V0fs (for example, 0V) is applied to the first node ND1 from a data line DTL through the write transistor TRW which has been turned on by a scanning signal from a scanning line SCL. According to this, a potential of the first node ND1 will be V0fs. A second node initialization voltage VCC-L (for example, −10V) is applied to a second node ND2 from a power supply unit 100 through the drive transistor TRD. According to this, a potential of the second node ND2 will be VCC-L. A threshold voltage of the drive transistor TRD is represented as a voltage Vth (for example, 3V). The voltage difference between the gate electrode and the other source/drain region of the drive transistor TRD (also referred to as a source region for convenience in the following description) is more than Vth, and the drive transistor TRD is in on-state.
Next, threshold voltage cancel processing is performed over a period from [Period-TP(2)1B] to [Period-TP(2)5]. Specifically, first threshold voltage cancel processing is performed in [Period-TP(2)1B]. Specifically, second threshold voltage cancel processing is performed in [Period-TP(2)3], then, third threshold voltage cancel processing is performed in [Period-TP(2)5].
In [Period-TP(2)1B], a voltage of the power supply unit 100 is switched from the second node initialization voltage VCC-L to a drive voltage VCC-H (for example, 20V) while maintaining on-state of the write transistor TRW. As a result, the potential of the second node ND2 is changed toward a potential obtained by subtracting the threshold voltage Vth of the drive transistor TRD from the potential of the first node ND1. That is, the potential of the second node ND2 is increased.
When [Period-TP(2)1B] is sufficiently long, the potential difference between the gate electrode and the other source/drain region of the drive transistor TRD reaches the threshold Vth, and the drive transistor TRD is turned off. That is, the potential of the second node ND2 becomes close to (Vofs−Vth) and finally becomes (Vofs−Vth). However, in the example shown in FIG. 4, the length of [Period-TP(2)1B] is not sufficient for changing the potential of the second node ND2 sufficiently, and the potential of the second node ND2 reaches a given potential V1 satisfying the relation VCC-L<V1<(Vofs−Vth) at the end of [Period-TP(2)1B].
At the beginning of [Period-TP(2)2], a voltage of the data line DTL is switched from the first node initialization voltage Vofs to a video signal VSig—m−2. The write transistor TRW is turned off by the signal from the scanning line SCL at the beginning of [Period-TP(2)2] so that the video signal VSig—m−2 is not applied to the first node ND1. As a result, the first node ND1 becomes in a floating state.
As the drive voltage VCC-H is applied to one source/drain region of the drive transistor TRD from the power supply unit 100, the potential of the second node ND2 is increased to a given potential V2 from the potential V1. On the other hand, the gate electrode of the drive transistor TRD is in the floating state and the capacitor unit C1 exists, therefore, a bootstrap operation is generated at the gate electrode of the drive transistor TRD. Accordingly, the potential of the first node ND1 is increased in accordance with potential change of the second node ND2.
At the beginning of [Period-TP(2)3], the voltage of the data line DTL is switched from the video signal VSig—m−2 to the first node initialization voltage Vofs. At the beginning of [Period-TP(2)3], the write transistor TRW is turned on by the signal from the scanning line SCL. As a result, the potential of the first node ND1 becomes Vofs. The drive voltage VCC-H is applied to one source/drain region of the drive transistor TRD from the power supply unit 100. As a result, the potential of the second node ND2 is changed toward a potential obtained by subtracting the threshold voltage Vth of the drive transistor TRD from the potential of the first node ND1. That is, the potential of the second node ND2 is increased from the potential V2 to a given potential V3.
At the beginning of [Period-TP(2)4], the voltage of the data line DTL is switched from the first node initialization voltage V0fs to a video signal VSig—m−1. At the beginning of [Period-TP(2)4], the write transistor TRW is turned off by the signal from the scanning line SCL so that the video signal VSig—m−1 is not applied to the first node ND1. As a result, the first node ND1 becomes in the floating state.
The drive voltage VCC-H is applied to one source/drain region of the drive transistor TRD from the power supply unit 100, therefore, the potential of the second node ND2 is increased from the potential V3 to a given potential V4. On the other hand, the gate electrode of the drive transistor TRD is in the floating state and there exists the capacitor unit C1, therefore, the bootstrap operation is generated at the gate electrode of the drive transistor TRD. Accordingly, the potential of the first node ND1 is increased in accordance with potential change of the second node ND2.
As a presupposition of an operation in [Period-TP(2)5], it is necessary that the potential V4 of the second node ND2 is lower than (Vofs−Vth) at the beginning of [Period-TP(2)5]. The length from the beginning of [Period-TP(2)1B] to the beginning of [Period-TP(2)5] is so determined as to satisfy a condition of V4<(Vofs-L−Vth)
The operation of [Period-TP(2)5] is basically the same as the operation explained in [Period-TP(2)3]. At the beginning of [Period-TP(2)5], the voltage of the data line DTL is switched from the video signal VSig—m−1 to the first node initialization voltage V0fs. At the beginning of [Period-TP(2)5], the write transistor TRW is turned on by the signal from the scanning line SCL.
The first node ND1 is in a state that the first node initialization voltage V0fs is applied from the data line DTL through the write transistor TRW. The drive voltage VCC-H is applied to one source/drain region of the drive transistor TRD from the power supply unit 100. As in the same manner as explained in [Period-TP(2)3], the potential of the second node ND2 is changed toward a potential obtained by subtracting the threshold voltage Vth of the drive transistor TRD from the potential of the first node ND1. When a potential difference between the gate electrode and the other source/drain region of the drive transistor TRD reaches Vth, the drive transistor TRD is turned off. In this state, the potential of the second node ND2 is almost (Vofs−Vth).
After that, in [Period-TP(2)6A], the write transistor TRW is turned off. Then, the voltage of the data line DTL is made to be a voltage corresponding to a video signal [Video signal (drive signal, luminance signal) VSig—m for controlling luminance in the light emitting portion ELP.
Next, in [Period-TP(2)6B], writing processing is performed. Specifically, the write transistor TRW is turned on by allowing the scanning line SCL to be high level. As a result, the potential of the first node ND1 is increased to the video signal VSig—m.
In the above operation, the video signal VSig—m is applied to the gate electrode of the drive transistor TRD in the state in which the drive voltage VCC-H is applied to one source/drain region of the drive transistor TRD from the power supply unit 100. Accordingly, as shown in FIG. 4, the potential of the second node ND2 is increased in [Period-TP(2)6B]. The increased amount ΔV of the potential (potential correction value) will be described later. When the potential of the gate electrode of the drive transistor TRD (first node ND1) is Vg and the potential of the other source/drain region (second node ND2) thereof is Vs, a value of Vg and a value of Vs will be as follows when the increased amount ΔV of the potential of the second node ND2 is not considered. A potential difference between the first node ND1 and the second node ND2, namely, a potential difference Vgs between the gate electrode of the drive transistor TRD and the other source/drain region functioning as a source region can be represented by the following formula (A).Vg=VSig—m Vs≅Vofs−Vth Vgs≅VSig—m−(Vofs−Vth)  (A)
That is, Vgs obtained in the writing processing with respect to the drive transistor TRD depends only on the video signal VSig—m for controlling the luminance in the light emitting portion ELP, the threshold voltage Vth of the drive transistor TRD and the voltage Vofs for initializing the potential of the gate electrode of the drive transistor TRD. Additionally, Vgs has no relation to a threshold voltage Vth-EL of the light emitting portion ELP.
Next, mobility correction processing will be briefly explained. In the above-described operation, mobility correction processing for changing the potential of the other source/drain region of the drive transistor TRD (namely, the potential of the second node ND2) in accordance with characteristics (for example, the size of mobility μ) of the drive transistor TRD is performed together with the writing processing.
As described above, the video signal VSig—m is applied to the gate electrode of the drive transistor TRD in the state in which the drive voltage VCC-H is applied to the one source/drain region of the drive transistor TRD from the power supply unit 100. Here, as shown in FIG. 4, the potential of the second node ND2 is increased in [Period-TP(2)6B]. As a result, when a value of the mobility μ of the drive transistor TRD is large, the increased amount ΔV of the potential (potential correction value) in the source region of the drive transistor TRD is increased. When the value of the mobility μ of the drive transistor TRD is small, the increased amount ΔV of the potential (potential correction value) in the source region of the drive transistor TRD is reduced. The potential difference Vgs between the gate electrode and the source region of the drive transistor TRD is deformed from the formula (A) to the following formula (B).Vgs≅VSig—m−(Vofs−Vth)−ΔV  (B)
According to the above operation, the threshold voltage cancel processing, the writing processing and the mobility correction processing are completed. Then, at the beginning of [Period-TP(2)6C] after that, the first node ND1 is allowed to be in the floating state by turning off the write transistor TRW based on the scanning signal from the scanning line SCL. One source/drain region (also referred to as a drain region for convenience in the following description) is in a state in which the drive voltage VCC-H is applied from the power supply unit 100. As the result of the above, the potential of the second node ND2 is increased and a phenomenon similar to a so-called bootstrap circuit is generated at the gate electrode of the drive transistor TRD, then, the potential of the first node NDD is increased. The potential difference Vgs between the gate electrode and the source region of the drive transistor TRD maintains the value of the formula (B). Electric current flowing through the light emitting portion ELP is a drain current Ids flowing from the drain region to the source region of the drive transistor TRD. When the drive transistor TRD ideally operates in a saturation region, the drain current Ids can be represented by the following formula (C). The light emitting portion ELP emits light corresponding to a value of the drain current Ids. A coefficient “k” will be described later.
                                                        Ids              =                            ⁢                              k                ·                µ                ·                                                      (                                                                  V                        gs                                            =                                              V                        th                                                              )                                    2                                                                                                        =                            ⁢                              k                ·                µ                ·                                                      (                                                                  V                        Sig_m                                            -                                              V                        ofs                                            -                                              Δ                        ⁢                                                                                                  ⁢                        V                                                              )                                    2                                                                                        (        C        )            
According to the above formula (C), the drain current Ids is in proportion to the mobility μ. On the other hand, the larger the mobility μ of the drive transistor TRD is, the larger the potential correction value ΔV becomes as well as the smaller a value of (VSig—m−Vofs−ΔV)2 in the formula (C) becomes. Accordingly, variations of the drain current Ids caused by variations the mobility μ of the drive transistor can be corrected.
Operations of the 2Tr/1C drive circuit the outline of which has been explained as the above will be explained later.